(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and specifically to a process used to simultaneously fabricate a capacitor structure and metal oxide semiconductor field effect transistors, (MOSFET), devices.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor chips, while still attempting to decrease the cost of these same semiconductor chips. These objectives have been partially realized via the trend to micro-miniaturization, or the ability of the semiconductor industry to fabricate semiconductor devices featuring sub-micron features. The use of sub-micron features result in smaller devices, reducing device capacitances and resistances, thus offering performance benefits. In addition the attainment of smaller chips, via micro-miniaturazation, allows a greater number of these smaller chips to be obtained from a specific size starting substrate, thus reducing the processing cost for a specific chip. The ability to create semiconductor devices with sub-micron features has resulted from advances in specific semiconductor fabrication disciplines, such as photolithography and reactive ion etching. For example the use of more advanced exposure cameras, as well as the use of more sensitive photoresist materials, have enabled sub-micron images to be routinely obtained in photoresist layers. In addition the development of more sophisticated dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in the creation of semiconductor devices.
Another method used to reduce the processing costs for semiconductor chips, is the technique of simultaneously fabricating the various device types needed for a specific semiconductor chip. For example logic and memory chips, used for static random access memory, (SRAM), dynamic random access memory, (DRAM), erasable electrically programmable read only memory, (EEPROM), cells, incorporate various semiconductor devices such as capacitors, resistors, diodes, as well as p-channel MOSFETS, (PFET), and n-channel MOSFET, (NFET), devices. The ability to simultaneously fabricate, and integrate these specific device types, simplifies, and reduces the cost of the fabrication process. One such design benefitting from the cost reducing, and simplified, integrated process is the design using a capacitor, in addition to both PFET and NFET devices. One polysilicon layer is used for the plate of the capacitor, as well as for the gate structure for both PFET and NFET devices. However in this design the capacitor dielectric, a silicon oxide layer grown on the underlying polysilicon plate, is exposed to a source and drain drive-in sequence, used for PFET and NFET processing. The drive-in, although performed in an non-oxidizing ambient, such as nitrogen, still presents a finite level of moisture or oxygen in the nitrogen gas or in the anneal furnace, which can result in an unwanted, and random increase in capacitor dielectric thickness, adversely influencing the attainment of the desired capacitor characteristics. This invention will present a process for integrating PFET and NFET devices, with capacitor structures, however using a structure and process which protects the capacitor dielectric from the effects of the source and drain drive-in ambient. In this invention a layer of silicon nitride is integrated into the capacitor structure, at a point in the process prior to the source and drain drive-in. Prior art, such as Sandhu, et al., in U.S. Pat. No. 5,376,593, describe a capacitor with dielectric layers of silicon nitride and silicon oxide, however without the integration of the PFET and NFET devices, and specifically without the drive-in cycles, which adversely influences the unprotected capacitor dielectric layer.